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CVE-2026-90124

Опубликовано: 19 сент. 2026
Источник: msrc
CVSS3: 7.1
EPSS Низкий

Описание

irqchip/renesas-rzg2l: Fix loss of interrupt

Обновления

ПродуктСтатьяОбновление
azl3 kernel 6.6.150.1-1 on Azure Linux 3.0

Показывать по

EPSS

Процентиль: 11%
0.00206
Низкий

7.1 High

CVSS3

Связанные уязвимости

ubuntu
4 дня назад

(In the Linux kernel, the following vulnerability has been resolved: i ...)

nvd
4 дня назад

In the Linux kernel, the following vulnerability has been resolved: irqchip/renesas-rzg2l: Fix loss of interrupt rzg2l_clear_irq_int() and rzg2l_clear_tint_int() perform a read-modify-write on the ISCR/TSCR status registers to clear the bit for the interrupt just handled. Since these registers are write-0-to-clear per bit, this is racy: If another interrupt's status bit gets set between the read and the write, that bit is written back as 0 by the software-constructed value, clearing an interrupt that hasn't been serviced yet and losing it. This can be reproduced by triggering multiple interrupts at once, e.g.: gpioset -c gpiochip0 355=0 353=0 328=0 352=0 Fix this by writing back only the bit being cleared, with all other bits set to 1, instead of read-modify-writing the whole register. Since 1-bits are left unchanged by hardware, concurrently-set status bits for other interrupts are preserved.

debian
4 дня назад

In the Linux kernel, the following vulnerability has been resolved: i ...

github
4 дня назад

In the Linux kernel, the following vulnerability has been resolved: irqchip/renesas-rzg2l: Fix loss of interrupt rzg2l_clear_irq_int() and rzg2l_clear_tint_int() perform a read-modify-write on the ISCR/TSCR status registers to clear the bit for the interrupt just handled. Since these registers are write-0-to-clear per bit, this is racy: If another interrupt's status bit gets set between the read and the write, that bit is written back as 0 by the software-constructed value, clearing an interrupt that hasn't been serviced yet and losing it. This can be reproduced by triggering multiple interrupts at once, e.g.: gpioset -c gpiochip0 355=0 353=0 328=0 352=0 Fix this by writing back only the bit being cleared, with all other bits set to 1, instead of read-modify-writing the whole register. Since 1-bits are left unchanged by hardware, concurrently-set status bits for other interrupts are preserved.

EPSS

Процентиль: 11%
0.00206
Низкий

7.1 High

CVSS3