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CVE-2026-89930

Опубликовано: 16 сент. 2026
Источник: nvd
CVSS3: 9.3
EPSS Низкий

Описание

In the Linux kernel, the following vulnerability has been resolved:

KVM: nVMX: Service local TLB flushes on failed nested VM-Enter

KVM services local TLB flushes on "full" nested VM-Exits (through __nested_vmx_vmexit()), but not if a nested VM-Enter fails (e.g. due to failed VMCS checks in nested_vmx_enter_non_root_mode()).

However, it is possible that KVM had queued TLB flushes that need to be performed, even if the nested VM-Enter was not successful. For example, if VPID is disabled for L2 (via nested_vmx_transition_tlb_flush(), or if via the MSR load lists, as the SDM says:

If any MSR is being loaded in such a way that would architecturally require a TLB flush, the TLBs are updated so that, after VM entry, the logical processor will not use any translations that were cached before the transition.

The SDM is unclear about when the TLB flush should occur, and whether or not a failed VM entry would flush the TLB, so it is safer to always do the TLB flush in this case.

Mor

EPSS

Процентиль: 8%
0.0018
Низкий

9.3 Critical

CVSS3

Дефекты

Связанные уязвимости

CVSS3: 9.3
ubuntu
5 дней назад

(In the Linux kernel, the following vulnerability has been resolved: K ...)

msrc
5 дней назад

KVM: nVMX: Service local TLB flushes on failed nested VM-Enter

CVSS3: 9.3
debian
6 дней назад

In the Linux kernel, the following vulnerability has been resolved: K ...

CVSS3: 9.3
github
6 дней назад

In the Linux kernel, the following vulnerability has been resolved: KVM: nVMX: Service local TLB flushes on failed nested VM-Enter KVM services local TLB flushes on "full" nested VM-Exits (through __nested_vmx_vmexit()), but not if a nested VM-Enter fails (e.g. due to failed VMCS checks in nested_vmx_enter_non_root_mode()). However, it is possible that KVM had queued TLB flushes that need to be performed, even if the nested VM-Enter was not successful. For example, if VPID is disabled for L2 (via nested_vmx_transition_tlb_flush(), or if via the MSR load lists, as the SDM says: If any MSR is being loaded in such a way that would architecturally require a TLB flush, the TLBs are updated so that, after VM entry, the logical processor will not use any translations that were cached before the transition. The SDM is unclear about when the TLB flush should occur, and whether or not a failed VM entry would flush the TLB, so it is safer to always do the TLB flush in this case. ...

EPSS

Процентиль: 8%
0.0018
Низкий

9.3 Critical

CVSS3

Дефекты