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CVE-2026-90243

Опубликовано: 17 сент. 2026
Источник: nvd
CVSS3: 8.1
EPSS Низкий

Описание

In the Linux kernel, the following vulnerability has been resolved:

iommu/vt-d: Clear Present bit before tearing down copied context entry

copied_context_tear_down() zeroes the 128-bit context entry with context_clear_entry() while the Present bit is still set, and only then issues the context-cache and IOTLB invalidations. This leaves a window in which hardware can fetch a torn entry, with some fields already zeroed while Present is still set, leading to unpredictable behaviour or spurious faults. While x86 provides strong write ordering, the compiler may reorder the writes to the two 64-bit halves of the entry, and the hardware fetch is not guaranteed to be atomic with respect to multiple CPU writes.

There is no cacheline flush before the invalidation either, so on an IOMMU without coherent access to the context table the zeroed entry may not be visible to hardware at the point the invalidation is submitted.

Apply the same ownership handshake described in the VT-d spec, Section

EPSS

Процентиль: 6%
0.00161
Низкий

8.1 High

CVSS3

Дефекты

Связанные уязвимости

CVSS3: 8.1
ubuntu
4 дня назад

(In the Linux kernel, the following vulnerability has been resolved: i ...)

CVSS3: 8.1
debian
4 дня назад

In the Linux kernel, the following vulnerability has been resolved: i ...

CVSS3: 8.1
github
4 дня назад

In the Linux kernel, the following vulnerability has been resolved: iommu/vt-d: Clear Present bit before tearing down copied context entry copied_context_tear_down() zeroes the 128-bit context entry with context_clear_entry() while the Present bit is still set, and only then issues the context-cache and IOTLB invalidations. This leaves a window in which hardware can fetch a torn entry, with some fields already zeroed while Present is still set, leading to unpredictable behaviour or spurious faults. While x86 provides strong write ordering, the compiler may reorder the writes to the two 64-bit halves of the entry, and the hardware fetch is not guaranteed to be atomic with respect to multiple CPU writes. There is no cacheline flush before the invalidation either, so on an IOMMU without coherent access to the context table the zeroed entry may not be visible to hardware at the point the invalidation is submitted. Apply the same ownership handshake described in the VT-d spec, Sect...

EPSS

Процентиль: 6%
0.00161
Низкий

8.1 High

CVSS3

Дефекты