Количество 9
Количество 9
BDU:2025-07529
Уязвимость компонента microchip-core ядра операционной системы Linux, позволяющая нарушителю вызвать отказ в обслуживании
CVE-2024-42279
In the Linux kernel, the following vulnerability has been resolved: spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer While transmitting with rx_len == 0, the RX FIFO is not going to be emptied in the interrupt handler. A subsequent transfer could then read crap from the previous transfer out of the RX FIFO into the start RX buffer. The core provides a register that will empty the RX and TX FIFOs, so do that before each transfer.
CVE-2024-42279
In the Linux kernel, the following vulnerability has been resolved: spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer While transmitting with rx_len == 0, the RX FIFO is not going to be emptied in the interrupt handler. A subsequent transfer could then read crap from the previous transfer out of the RX FIFO into the start RX buffer. The core provides a register that will empty the RX and TX FIFOs, so do that before each transfer.
CVE-2024-42279
In the Linux kernel, the following vulnerability has been resolved: spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer While transmitting with rx_len == 0, the RX FIFO is not going to be emptied in the interrupt handler. A subsequent transfer could then read crap from the previous transfer out of the RX FIFO into the start RX buffer. The core provides a register that will empty the RX and TX FIFOs, so do that before each transfer.
CVE-2024-42279
In the Linux kernel, the following vulnerability has been resolved: s ...
GHSA-g2mq-v2g4-xgcx
In the Linux kernel, the following vulnerability has been resolved: spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer While transmitting with rx_len == 0, the RX FIFO is not going to be emptied in the interrupt handler. A subsequent transfer could then read crap from the previous transfer out of the RX FIFO into the start RX buffer. The core provides a register that will empty the RX and TX FIFOs, so do that before each transfer.
SUSE-SU-2024:3195-1
Security update for the Linux Kernel
SUSE-SU-2024:3383-1
Security update for the Linux Kernel
SUSE-SU-2024:3194-1
Security update for the Linux Kernel
Уязвимостей на страницу
Уязвимость | CVSS | EPSS | Опубликовано | |
|---|---|---|---|---|
 | BDU:2025-07529 Уязвимость компонента microchip-core ядра операционной системы Linux, позволяющая нарушителю вызвать отказ в обслуживании | CVSS3: 8 | 0% Низкий | больше 1 года назад |
 | CVE-2024-42279 In the Linux kernel, the following vulnerability has been resolved: spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer While transmitting with rx_len == 0, the RX FIFO is not going to be emptied in the interrupt handler. A subsequent transfer could then read crap from the previous transfer out of the RX FIFO into the start RX buffer. The core provides a register that will empty the RX and TX FIFOs, so do that before each transfer. | CVSS3: 5.5 | 0% Низкий | больше 1 года назад |
 | CVE-2024-42279 In the Linux kernel, the following vulnerability has been resolved: spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer While transmitting with rx_len == 0, the RX FIFO is not going to be emptied in the interrupt handler. A subsequent transfer could then read crap from the previous transfer out of the RX FIFO into the start RX buffer. The core provides a register that will empty the RX and TX FIFOs, so do that before each transfer. | CVSS3: 5.8 | 0% Низкий | больше 1 года назад |
 | CVE-2024-42279 In the Linux kernel, the following vulnerability has been resolved: spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer While transmitting with rx_len == 0, the RX FIFO is not going to be emptied in the interrupt handler. A subsequent transfer could then read crap from the previous transfer out of the RX FIFO into the start RX buffer. The core provides a register that will empty the RX and TX FIFOs, so do that before each transfer. | CVSS3: 5.5 | 0% Низкий | больше 1 года назад |
| CVE-2024-42279 In the Linux kernel, the following vulnerability has been resolved: s ... | CVSS3: 5.5 | 0% Низкий | больше 1 года назад |
| GHSA-g2mq-v2g4-xgcx In the Linux kernel, the following vulnerability has been resolved: spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer While transmitting with rx_len == 0, the RX FIFO is not going to be emptied in the interrupt handler. A subsequent transfer could then read crap from the previous transfer out of the RX FIFO into the start RX buffer. The core provides a register that will empty the RX and TX FIFOs, so do that before each transfer. | CVSS3: 5.5 | 0% Низкий | больше 1 года назад |
 | SUSE-SU-2024:3195-1 Security update for the Linux Kernel | больше 1 года назад | ||
| SUSE-SU-2024:3383-1 Security update for the Linux Kernel | больше 1 года назад | ||
| SUSE-SU-2024:3194-1 Security update for the Linux Kernel | больше 1 года назад |
Уязвимостей на страницу